CV - Sushant Mondal

Summarized objective

My work spans computer architecture, hardware verification, and server hosting (IaaS). Currently building and verifying my own RISC-V CPU.

Co-Founder, Computer Architect, and Logic Researcher

August 2026–Present

Renvatek Microelectronics, Jabalpur, Madhya Pradesh, India

Co-Founder and System Administrator

September 2024–Present

FireVM.com Hosting, Jabalpur, Madhya Pradesh, India

Managed infrastructure (IaaS), cloud computing, hosting operations, and client service workflows for VPSs, dedicated servers, and reseller-hosting environments running AlmaLinux (RHEL-based), including package and system administration.
Set up the company’s entire billing system using WHMCS.
Administered Linux hosting with control panels including cPanel/WHM, Plesk, and Webmin/Virtualmin.
Managed automated domain registration using WHMCS and ResellerClub reseller backend.
Built the company website using WordPress, Elementor, and custom CSS.
Used JetBackup to automate backups of clients’ control panels over multiple backup servers.
Monitored the colossal network of servers using Zabbix.

RV32I-based, single-cycle CPU

January 2026–Present

Studied the fundamentals of computer architecture and engineering.
Stored the entire codebase in a private and self-hosted Git server running GitLab as the frontend.
Holy Core Project (Single-Cycle Edition) April 2026–July 2026

Ex-Contributor
PRs and issues consisted of (and were not limited to):
- Fixed many critical logical and datapath-related issues (which were failing RISC-V compliance).
- Reformatted SystemVerilog code according to lowRISC Verilog Style Guide.
- Removed redundant code from SystemVerilog files.
- Removed outdated decorators from cocotb Python testbench files.
[WIP]

SystemVerilog (intermediate)

Worked on RTL design and verification.
Developed an understanding of core HDL concepts and testbench development.
Familiar with synthesizable logic design, excluding UVM and object-oriented methodologies.
Wrote consistent code using the lowRISC Verilog Style Guide.

Python (intermediate)

Top 0.5% consistent academic ranking April 2019–March 2027

Mount Litera Zee School
St. Aloysius Senior Secondary School
1400/1600 (93rd percentile) in Digital SAT® November 2025

Reading and Writing: 640/800 (83rd percentile)
Math: 760/800 (96th percentile)
College Board
95.8% (top 2% nationally) in Grade 10 CBSE board examinations May 2025

Mount Litera Zee School
6/58 rank in the Inter-School Chess Tournament November 2024

M.K. Chess Academy
Two-time intra-school chess gold medalist January 2022 and September 2024

Mount Litera Zee School
Student of the Year April 2019–March 2020

St. Aloysius Senior Secondary School