How to start writing HDL, like SystemVerilog, as a total beginner

A while back, late February this year, I started to build my single-cycle RISC-V (XLEN=32) CPU. The only problem was this: I did not know anything about CPUs, their internals, or where to start or how.

Let me tell you a very important thing: do not chase any course, paid ones especially, to “learn” how to build your first RTL project. When I started, I did not even know the syntax of SystemVerilog, let alone know how to write RTL files.

The only way to actually make your project is to watch some YouTube videos or playlists and browse through simple RTL repositories.

After a while, it will eventually click for you that when someone says to “write HDL,” they particularly mean that you have to describe the hardware using code, i.e., the HDL.

Basically, we have to define in code the stuff you experimented with using low-level gates back in Logisim Evolution. Let me explain this using Logisim Evolution’s analogy.

Modules and ports are like the I/O pins (ports) you use inside Logisim Evolution subcircuits (modules).

module subcircuit (
  input  logic [1:0] pin1_i
  output logic [1:0] pin2_o
);

  // Compute here, i.e., this subcircuit's tasks.
  // You also can declare internal wires that stay inside this subcircuit and never leave it.
  module_contents;

endmodule : subcircuit

See? This way, you can just “see” someone else’s code, learn the HDL’s syntax, and make your first project by taking theirs as a reference.