{"id":77,"date":"2026-07-13T12:24:09","date_gmt":"2026-07-13T06:54:09","guid":{"rendered":"https:\/\/www.sushantmondal.com\/blog\/?p=77"},"modified":"2026-09-01T17:24:51","modified_gmt":"2026-09-01T11:54:51","slug":"how-to-start-writing-hdl-like-systemverilog-as-a-total-beginner","status":"publish","type":"post","link":"https:\/\/www.sushantmondal.com\/blog\/2026\/07\/13\/how-to-start-writing-hdl-like-systemverilog-as-a-total-beginner\/","title":{"rendered":"How to start writing HDL, like SystemVerilog, as a total beginner"},"content":{"rendered":"\n<p class=\"wp-block-paragraph\">A while back, late February this year, I started to build my single-cycle RISC-V (<code>XLEN=32<\/code>) CPU. The only problem was this: I did not know anything about CPUs, their internals, or where to start or how.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Let me tell you a very important thing: do <em>not<\/em> chase any course, paid ones especially, to &#8220;learn&#8221; how to build your first RTL project. When I started, I did not even know the syntax of SystemVerilog, let alone know how to write RTL files.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><em>The only way to actually make your project is to watch some YouTube videos or playlists and browse through simple RTL repositories.<\/em><\/p>\n\n\n\n<p class=\"wp-block-paragraph\">After a while, it will eventually click for you that when someone says to &#8220;write HDL,&#8221; they particularly mean that you have to describe the hardware using code, i.e., the HDL.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Basically, we have to define in code the stuff you experimented with using low-level gates back in <a href=\"https:\/\/www.github.com\/logisim-evolution\/logisim-evolution\/\" target=\"_blank\" rel=\"noreferrer noopener nofollow\">Logisim Evolution<\/a>. Let me explain this using Logisim Evolution&#8217;s analogy.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Modules and ports are like the I\/O pins (ports) you use inside Logisim Evolution subcircuits (modules).<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>module subcircuit (\n  input  logic &#91;1:0] pin1_i\n  output logic &#91;1:0] pin2_o\n);\n\n  \/\/ Compute here, i.e., this subcircuit's tasks.\n  \/\/ You also can declare internal wires that stay inside this subcircuit and never leave it.\n  module_contents;\n\nendmodule : subcircuit<\/code><\/pre>\n\n\n\n<p class=\"wp-block-paragraph\">See? This way, you can just &#8220;see&#8221; someone else&#8217;s code, learn the HDL&#8217;s syntax, <em>and<\/em> make your first project by taking theirs as a reference.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Skip paid courses. Learn SystemVerilog and HDL basics by reading real RTL code and watching YouTube tutorials instead.<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"pagelayer_contact_templates":[],"_pagelayer_content":"","inline_featured_image":false,"_jetpack_newsletter_access":"","_jetpack_dont_email_post_to_subs":false,"_jetpack_newsletter_tier_id":0,"_jetpack_memberships_contains_paywalled_content":false,"_jetpack_feature_clip_id":0,"_jetpack_memberships_contains_paid_content":false,"footnotes":"","jetpack_post_was_ever_published":false},"categories":[9],"tags":[14,12,13,10,11],"class_list":["post-77","post","type-post","status-publish","format-standard","hentry","category-hardware","tag-computer-architecture","tag-logisim-evolution","tag-risc-v","tag-rtl","tag-systemverilog"],"jetpack_sharing_enabled":true,"jetpack_likes_enabled":true,"jetpack_featured_media_url":"","_links":{"self":[{"href":"https:\/\/www.sushantmondal.com\/blog\/wp-json\/wp\/v2\/posts\/77","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.sushantmondal.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.sushantmondal.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.sushantmondal.com\/blog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.sushantmondal.com\/blog\/wp-json\/wp\/v2\/comments?post=77"}],"version-history":[{"count":9,"href":"https:\/\/www.sushantmondal.com\/blog\/wp-json\/wp\/v2\/posts\/77\/revisions"}],"predecessor-version":[{"id":192,"href":"https:\/\/www.sushantmondal.com\/blog\/wp-json\/wp\/v2\/posts\/77\/revisions\/192"}],"wp:attachment":[{"href":"https:\/\/www.sushantmondal.com\/blog\/wp-json\/wp\/v2\/media?parent=77"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.sushantmondal.com\/blog\/wp-json\/wp\/v2\/categories?post=77"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.sushantmondal.com\/blog\/wp-json\/wp\/v2\/tags?post=77"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}